Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs

Koki Abe, Masataka Ishihara, Yusuke Hatakenaka, Kazuhiro Umetani, Eiji Hiraki. Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs. In 30th IEEE International Symposium on Industrial Electronics, ISIE 2021, Kyoto, Japan, June 20-23, 2021. pages 1-5, IEEE, 2021. [doi]

@inproceedings{AbeIHUH21,
  title = {Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs},
  author = {Koki Abe and Masataka Ishihara and Yusuke Hatakenaka and Kazuhiro Umetani and Eiji Hiraki},
  year = {2021},
  doi = {10.1109/ISIE45552.2021.9576373},
  url = {https://doi.org/10.1109/ISIE45552.2021.9576373},
  researchr = {https://researchr.org/publication/AbeIHUH21},
  cites = {0},
  citedby = {0},
  pages = {1-5},
  booktitle = {30th IEEE International Symposium on Industrial Electronics, ISIE 2021, Kyoto, Japan, June 20-23, 2021},
  publisher = {IEEE},
  isbn = {978-1-7281-9023-5},
}