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Evaluation of a Low-Power Reconfigurable DSP Architecture

Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marlene Wan, Jan M. Rabaey. Evaluation of a Low-Power Reconfigurable DSP Architecture. In 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP 98), March 30 - April 3, 1998, Orlando, Florida, USA, Proceedings. pages 55-60, IEEE Computer Society, 1998.

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Arthur Abnous

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Katsunori Seno

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Yuji Ichikawa

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Marlene Wan

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Jan M. Rabaey

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