Evaluation of a Low-Power Reconfigurable DSP Architecture

Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marlene Wan, Jan M. Rabaey. Evaluation of a Low-Power Reconfigurable DSP Architecture. In 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP 98), March 30 - April 3, 1998, Orlando, Florida, USA, Proceedings. pages 55-60, IEEE Computer Society, 1998.

Abstract

Abstract is missing.