Performance analysis of cosimulating processor core in VHDL and SystemC

Syed Saif Abrar, Maksim Jenihhin, Jaan Raik, Shyam Kiran A., C. Babu. Performance analysis of cosimulating processor core in VHDL and SystemC. In International Conference on Advances in Computing, Communications and Informatics, ICACCI 2013, Mysore, India, August 22-25, 2013. pages 563-568, IEEE, 2013. [doi]

Authors

Syed Saif Abrar

This author has not been identified. Look up 'Syed Saif Abrar' in Google

Maksim Jenihhin

This author has not been identified. Look up 'Maksim Jenihhin' in Google

Jaan Raik

This author has not been identified. Look up 'Jaan Raik' in Google

Shyam Kiran A.

This author has not been identified. Look up 'Shyam Kiran A.' in Google

C. Babu

This author has not been identified. Look up 'C. Babu' in Google