Trio Adiono, Mahendra Drajat Adhinata, Novi Prihatiningrum, Ricky Disastra, Rachmad Vidya Wicaksana Putra, Amy Hamidah Salman. An architecture design of SAD based template matching for fast queue counter in FPGA. In International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2016, Phuket, Thailand, October 24-27, 2016. pages 1-4, IEEE, 2016. [doi]
Abstract is missing.