Circuit optimization using statistical static timing analysis

Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov. Circuit optimization using statistical static timing analysis. In William H. Joyner Jr., Grant Martin, Andrew B. Kahng, editors, Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005. pages 321-324, ACM, 2005. [doi]

@inproceedings{AgarwalCBZ05,
  title = {Circuit optimization using statistical static timing analysis},
  author = {Aseem Agarwal and Kaviraj Chopra and David Blaauw and Vladimir Zolotov},
  year = {2005},
  doi = {10.1145/1065579.1065663},
  url = {http://doi.acm.org/10.1145/1065579.1065663},
  tags = {optimization, analysis, static analysis},
  researchr = {https://researchr.org/publication/AgarwalCBZ05},
  cites = {0},
  citedby = {0},
  pages = {321-324},
  booktitle = {Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005},
  editor = {William H. Joyner Jr. and Grant Martin and Andrew B. Kahng},
  publisher = {ACM},
  isbn = {1-59593-058-2},
}