Amit Agarwal, Kaushik Roy. A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. In Ingrid Verbauwhede, Hyung Roh, editors, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003. pages 18-21, ACM, 2003. [doi]
@inproceedings{AgarwalR03,
title = {A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime},
author = {Amit Agarwal and Kaushik Roy},
year = {2003},
doi = {10.1145/871506.871514},
url = {http://doi.acm.org/10.1145/871506.871514},
tags = {caching, design},
researchr = {https://researchr.org/publication/AgarwalR03},
cites = {0},
citedby = {0},
pages = {18-21},
booktitle = {Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003},
editor = {Ingrid Verbauwhede and Hyung Roh},
publisher = {ACM},
isbn = {1-58113-682-X},
}