A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime

Amit Agarwal, Kaushik Roy. A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. In Ingrid Verbauwhede, Hyung Roh, editors, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003. pages 18-21, ACM, 2003. [doi]

Abstract

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