Half-Precision Floating-Point Multiplier IP Core Based on 130 Nm CMOS ASIC Technology

Cuauhtémoc R. Aguilera-Galicia, Omar Lonuoria-Gandara, Luis Pizano-Escalante. Half-Precision Floating-Point Multiplier IP Core Based on 130 Nm CMOS ASIC Technology. In Ramiro Velázquez, Andrea Rodríguez, Carlos A. Gutiérrez, editors, 10th IEEE Latin-American Conference on Communications, LATINCOM 2018, Guadalajara, Jalisco, Mexico, November 14-16, 2018. pages 1-5, IEEE, 2018. [doi]

Abstract

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