On minimization of test power through modified scan flip-flop

Satyadev Ahlawat, Jaynarayan T. Tudu. On minimization of test power through modified scan flip-flop. In 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016. pages 1-6, IEEE, 2016. [doi]

Authors

Satyadev Ahlawat

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Jaynarayan T. Tudu

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