Abstract is missing.
- FPGA implementation of high speed reconfigurable filter bank for multi-standard wireless communication receiversSasha Garg, Sumit Jagdish Darak. 1-5 [doi]
- EG0N: Portable in-situ energy measurement for low-power sensor devicesNils Heitmann, Philipp Kindt, Samarjit Chakraborty. 1-6 [doi]
- Temperature dependent IR-drop and delay analysis in side-contact multilayer graphene nanoribbon based power interconnectsSandip Bhattacharya, Debaprasad Das, Hafizur Rahaman. 1-2 [doi]
- Performance analysis of temperature dependent GNR interconnectWaikhom Mona Chanu, Vikash Prasad, Debaprasad Das. 1-5 [doi]
- Backward compatible MIL-STD-1553B analog transceiver upgrade for 100-Mb/s data ratePrateek Pendyala, Vijaya Sankara Rao Pasupureddi. 1-5 [doi]
- Design methodology of closed loop MEMS capacitive accelerometers based on ΣΔ modulation techniqueProcheta Chatterjee, Sougata Kar, Siddhartha Sen 0002. 1-6 [doi]
- Guided shifting of test pattern to minimize test time in serial scanJaynarayan T. Tudu, Satyadev Ahlawat. 1-6 [doi]
- An 8-bit 500 MSPS segmented current steering DAC using Chinese abacus techniqueSachin Khandagale, Santanu Sarkar. 1-2 [doi]
- An area and performance aware ECG encoder design for wireless healthcare servicesBharat Garg, Sameer Yadav, G. K. Sharma. 1-6 [doi]
- Reducing FIFO buffer power using architectural alternatives at RTLAshish Sharma, Ruby Ansar, Manoj Singh Gaur, Lava Bhargava, Vijay Laxmi. 1-2 [doi]
- Formal verification of switched capacitor DC to DC power converter using circuit simulation tracesAmbuj Mishra, Subir K. Roy. 1-2 [doi]
- Design of fault tolerant majority voter for TMR circuit in QCASubrata Chattopadhyay, Shiv Bhushan Tripathi, Mrinal Goswami, Bibhash Sen. 1-2 [doi]
- Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary codingMohd Tasleem Khan, Shaik Rafi Ahamed, Amitabh Chatterjee. 1-6 [doi]
- Skip-scan: A methodology for test time reductionBinod Kumar 0001, Boda Nehru, Brajesh Pandey, Jaynarayan T. Tudu. 1-6 [doi]
- Synthesis aware sample preparation techniques using random sample sets in DMFBPranab Roy, Sudeshna Chakraborty, Hafizur Rahaman. 1-6 [doi]
- Golden IC free methodology for hardware Trojan detection using symmetric path delaysRamakrishna Vaikuntapu, Lava Bhargava, Vineet Sahula. 1-2 [doi]
- Towards a dynamic associativity enabled write prediction based hybrid cacheSukarn Agarwal, Hemangee K. Kapoor. 1-6 [doi]
- FSK demodulator and FPGA based BER measurement system for low IF receiversK. Nithin Sankar, Abhishek Srivastava, Baibhab Chatterjee, K. K. Rakesh, Maryam Shojaei Baghini. 1-2 [doi]
- An efficient reversible cryptographic circuit designBikromadittya Mondal, Kushal Dey, Susanta Chakraborty. 1-6 [doi]
- Cognitive-radio wireless-sensor based on energy detection with improved accuracy: Performance and hardware perspectivesRahul Shrestha, Vinay Swargam, Mahesh S. Murty. 1-6 [doi]
- T-Gate: Concept of partial polarization in Quantum Dot Cellular AutomataChiradeep Mukherjee, Soudip Sinha Roy, Saradindu Panda, Bansibadan Maji. 1-6 [doi]
- High performance bit-sliced pipelined comparator tree for FPGAsAyan Palchaudhuri, Anindya Sundar Dhar. 1-6 [doi]
- New stable loadless 6T dual-port SRAM cell designAntara Ganguly, Sangeeta Goyal, Sneha Bhatia, Anuj Grover. 1-6 [doi]
- Design and measurement techniques for a low noise amplifier in a receiver chain for MedRadio spectrum of 401-406 MHz frequency bandAbhishek Srivastava, Nithin Sankar, K. K. Rakesh, Baibhab Chatterjee, Devarshi Das, Maryam Shojaei Baghini. 1-6 [doi]
- A high CMRR, high resolution bio-ASIC for ECG signalsKiran Garje, Shravan Kumar, Amitesh Tripathi, Gillela Maruthi, Madhava Kumar. 1-2 [doi]
- A novel low power 6-bit FLASH ADC using charge steering amplifier for RF applicationsKrishna Kumar Movva, Syed Azeemuddin. 1-2 [doi]
- On determination of instantaneous peak and cycle peak switching using ILPRohini Gulve, Nihar Hage, Jaynarayan Tudu. 1-6 [doi]
- SAT: A new application mapping method for power optimization in 2D - NoCAravindhan Alagarsamy, Lakshminaraynan Gopalakrishnan. 1-6 [doi]
- BDD based synthesis technique for design of high-speed memristor based circuitsAnindita Chakraborty, Rakesh Das, Chandan Bandyopadhyay, Hafizur Rahaman. 1-6 [doi]
- Tag only storage for capacity optimised last level cache in chip multiprocessorsSurajit Das, Shirshendu Das, Hemangee K. Kapoor. 1-6 [doi]
- Synthesis of scheduler automata guaranteeing stability and reliability of embedded control systemsSaurav Kumar Ghosh, Akash Mondal, Souradeep Dutta, Aritra Hazra, Soumyajit Dey. 1-6 [doi]
- Optimal design flow of CMOS doubler-based rectifiersSoumik Sarkar, Gaurav Saini, Mahima Arrawatia, Maryam Shojaei Baghini. 1-6 [doi]
- Density gradient quantum corrections based performance optimization of triangular TG bulk FinFETs using ANN and GAAnkit Gaurav, Sandeep S. Gill, Navneet Kaur, Munish Rattan. 1-5 [doi]
- An effective and efficient algorithm to analyse and debug clock propagation issuesPawan Sehgal, Aditi Sharma, Akhilesh C. Mishra, Rangarajan Ramanujam, Sujay Deb. 1-6 [doi]
- Data dependent spurious power reduction for fixed width multiplierBharti Navlani, Pankaj U. Joshi, Raghavendra B. Deshmukh. 1-2 [doi]
- Analysis of regeneration time constant of dynamic latch using Adomian Decomposition methodA. Purushothaman. 1-6 [doi]
- On minimization of test power through modified scan flip-flopSatyadev Ahlawat, Jaynarayan T. Tudu. 1-6 [doi]
- Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoCMoumita Chakraborty, Amlan Chakrabarti, Partha Mitra, Debasri Saha, Krishnendu Guha. 1-6 [doi]
- Design of coherence verification unit for CMPs realizing dragon protocolBidesh Chakraborty, Mamata Dalui, Biplab K. Sikdar. 1-6 [doi]
- Variability and reliability aware surrogate model for sensing delay analysis of SRAM sense amplifierSapna Khandelwal, Jyoti Meena, Lokesh Garg, Dharmendar Boolchandani. 1-6 [doi]
- Programmable output switched capacitor step-down DC-DC converter with high accuracy using Sigma-Delta Feedback Control LoopMahesh Zanwar, Subhajit Sen. 1-6 [doi]
- Design, integration and performance analysis of ΣΔ ADC for capacitive sensor interfacingProcheta Chatterjee, Sougata Kar, Siddhartha Sen 0002. 1-2 [doi]
- JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and powerJaynarayan Tudu. 1-6 [doi]
- FFT/IFFT implementation using Vivado™ HLSAmit Salaskar, Nitin Chandrachoodan. 1-2 [doi]
- A constraint driven technique for MOS amplifier designParomita Bhattacharjee, Abir J. Mondal, Alak Majumder. 1-6 [doi]
- A low-power high-speed hybrid full adderManan Mewada, Mazad Zaveri. 1-2 [doi]
- Hardware optimizations for crypto implementations (Invited paper)M. Mohamed Asan Basiri, Sandeep K. Shukla. 1-6 [doi]
- Guided multilevel approximation of less significant bits for power reductionD. Celia, Nitin Chandrachoodan. 1-6 [doi]
- Modeling and yield estimation of SRAM sub-system for different capacities subjected to parametric variationsPulkit Sharma, Anil Kumar Gundu, M. S. Hashmi. 1-6 [doi]
- New technique to improve transient response of LDO regulators without an off-chip capacitorChetan D. Parikh, Gopal Agarwal. 1-5 [doi]
- An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOINidhi Batra, Anil Kumar Gundu, Mohammad S. Hashmi, G. S. Visweswaran, Anuj Grover. 1-6 [doi]
- An efficient FPGA-based function profiler for embedded system applicationsPavan Kumar Nadimpalli, Subir K. Roy. 1-6 [doi]
- Planning based guided reconstruction of corner cases in architectural validationRajib Lochan Jana, Shashank Kuchibhotla, Soumyajit Dey, Pallab Dasgupta, Rakesh Kumar. 1-6 [doi]
- A strategy for fault tolerant reconfigurable Network-on-Chip designNavonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay. 1-2 [doi]
- A FSM based approach for efficient implementation of K-means algorithmRahul Ratnakumar, Satyasai Jagannath Nanda. 1-6 [doi]
- A high speed low voltage latch type sense amplifier for non-volatile memoryDisha Arora, Anil Kumar Gundu, Mohammad S. Hashmi. 1-5 [doi]
- A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulationOm. Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas. 1-6 [doi]
- Approximate conditional carry adder for error tolerant applicationsAvishek Sinha Roy, N. Prasad, Anindya Sundar Dhar. 1-6 [doi]
- A low-cost energy efficient image scaling processor for multimedia applicationsBharat Garg, V. N. S. K. Chaitanya Goteti, G. K. Sharma. 1-6 [doi]
- A Pre-RTL floorplanner tool for automated CMP design space exploration with thermal awarenessSri Harsha Gade, Praveen Kumar, Sujay Deb. 1-6 [doi]
- A method to design a comparator for sampled data processing applicationsRama Prasad Acharya, Abir J. Mondal, Alak Majumder. 1-6 [doi]
- Smart handheld platform for electrochemical bio sensorsSuraj Hebbar, Vinay Kumar, M. S. Bhat, Navakanta Bhat. 1-2 [doi]
- Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cellPulkit Sharma, R. Anusha, K. Bharath, Jasmine Kaur Gulati, Preet K. Walia, Sumit Jagdish Darak. 1-2 [doi]
- Energy-efficient reconfigurable framework for evaluating hybrid NoCsRaghav Kishore, Hemanta Kumar Mondal, Sujay Deb. 1-2 [doi]
- Switched-capacitor circuit simulator in Q-V domain including nonidealitiesG. Muralidhar, Dinesh G., Binsu J. Kailath. 1-6 [doi]
- A robust 8T FinFET SRAM cell with improved stability for low voltage applicationsC. B. Kushwah, Devesh Dwivedi, N. Sathisha, Krishnan S. Rengarajan. 1-6 [doi]
- Frequency domain analysis of on-chip power distribution networkS. Batra, P. Singh, S. Kaushik, M. S. Hashmi. 1-6 [doi]
- Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoffDebasis Pal, Abir Pramanik, Parthasarathi Dasgupta, Debesh Kumar Das. 1-6 [doi]
- A mismatch insensitive reconfigurable discrete time biosignal conditioning circuit in 180 nm MM CMOS technologyPriyanka Kimtee, Devarshi Mrinal Das, Maryam Shojaei Baghini. 1-2 [doi]