A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation

Om. Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas. A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. In 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016. pages 1-6, IEEE, 2016. [doi]

Abstract

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