A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications

Hyun-A. Ahn, Yoo-Chang Sung, Yong Hun Kim, Janghoo Kim, Kihan Kim, Donghun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Garam Choi, Jun Seo Park, Bo-Hyeon Lee, Jin-Hyeok Baek, Daesik Moon, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Changsik Yoo, Tae-young Oh. A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2023, Haikou, China, November 5-8, 2023. pages 1-4, IEEE, 2023. [doi]

@inproceedings{AhnSKKKLGLJKCPLBMLBSYO23,
  title = {A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications},
  author = {Hyun-A. Ahn and Yoo-Chang Sung and Yong Hun Kim and Janghoo Kim and Kihan Kim and Donghun Lee and Young-Gil Go and Jae-Woo Lee and Jae-Woo Jung and Yong-Hyun Kim and Garam Choi and Jun Seo Park and Bo-Hyeon Lee and Jin-Hyeok Baek and Daesik Moon and Daihyun Lim and Seung-Jun Bae and Young-Soo Sohn and Changsik Yoo and Tae-young Oh},
  year = {2023},
  doi = {10.1109/A-SSCC58667.2023.10348005},
  url = {https://doi.org/10.1109/A-SSCC58667.2023.10348005},
  researchr = {https://researchr.org/publication/AhnSKKKLGLJKCPLBMLBSYO23},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2023, Haikou, China, November 5-8, 2023},
  publisher = {IEEE},
  isbn = {979-8-3503-3003-8},
}