Response of transport triggered architectures for high-speed processor design

S. M. Shamsul Alam, GoangSeog Choi. Response of transport triggered architectures for high-speed processor design. IEICE Electronic Express, 10(5):20120878, 2013. [doi]

@article{AlamC13-0,
  title = {Response of transport triggered architectures for high-speed processor design},
  author = {S. M. Shamsul Alam and GoangSeog Choi},
  year = {2013},
  doi = {10.1587/elex.10.20120878},
  url = {http://dx.doi.org/10.1587/elex.10.20120878},
  researchr = {https://researchr.org/publication/AlamC13-0},
  cites = {0},
  citedby = {0},
  journal = {IEICE Electronic Express},
  volume = {10},
  number = {5},
  pages = {20120878},
}