Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing - researchr publication authors

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Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky. Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. In Proceedings of the ASPDAC 2002 / VLSI Design 2002, CD-ROM, 7-11 January 2002, Bangalore, India. pages 580, IEEE Computer Society, 2002. [doi]

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