V. Aleshina, S. Frolov, M. Makarceva, A. Golenkevich. Synthesis of combinational circuits from the truth tables in "Kovcheg" CAD design flow. In 2016 IEEE East-West Design & Test Symposium, EWDTS 2016, Yerevan, Armenia, October 14-17, 2016. pages 1-4, IEEE, 2016. [doi]
Abstract is missing.