Jaafar Alghazo, Nazeih Botros. Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs. In Laurence Tianruo Yang, Hamid R. Arabnia, Yiming Li, Salam N. Salloum, José G. Delgado-Frias, editors, Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005. pages 136-142, CSREA Press, 2005.
@inproceedings{AlghazoB05,
title = {Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs},
author = {Jaafar Alghazo and Nazeih Botros},
year = {2005},
tags = {modeling},
researchr = {https://researchr.org/publication/AlghazoB05},
cites = {0},
citedby = {0},
pages = {136-142},
booktitle = {Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005},
editor = {Laurence Tianruo Yang and Hamid R. Arabnia and Yiming Li and Salam N. Salloum and José G. Delgado-Frias},
publisher = {CSREA Press},
isbn = {1-932415-54-8},
}