Abstract is missing.
- Proactive Fault Monitoring in Enterprise ServersKeith Whisnant, Kenny C. Gross, Natasha Lingurovska. 3-10
- Estimation of Architectural Vulnerability Factors for Discrimination of Single Event Upsets in Cache MemoryAnton Bougaev, Brian Mariner, Joshua Walter. 11-20
- Fault Modeling and Testability of CMOS Domino CircuitsWaleed Al-Assadi, Pavankumar Chandrasekhar, Bonita Bhaskaran. 21-27
- Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOSDaniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias. 28-34
- High-Speed Energy Estimation for Delay-Insensitive CircuitsBonita Bhaskaran, Venkat Satagopan, Scott C. Smith. 35-41
- High-Performance Double-Precision Cosine GenerationDerek Nowrouzezahrai, Brian Decker, William Bishop. 42-48
- Design of PCI 2.2 Target Controller to Support Prefetch RequestEugin Hyun, Kyo-Yong Han, Kwang-Su Seong. 49-58
- Implementation of Network Systems Using Network Processor Technology: Performance EvaluationKoert Vlaeminck, Tim Stevens, Wim Van de Meerssche, Filip De Turck, Bart Dhoedt, Piet Demeester. 59-63
- Modeling and Verification of a Distributed Transmission ProtocolLubomir Ivanov. 64-70
- Design and Verification of I/O Controller for Future Communication SystemEugin Hyun, Kwang-Su Seong. 71-77
- Implementation of Design For Test for Asynchronous NCL DesignsBonita Bhaskaran, Venkat Satagopan, Waleed Al-Assadi, Scott C. Smith. 78-84
- Verilog Coding Style for Efficient Synthesis In FPGAHimanshu Thapliyal, M. B. Srinivas, Rameshwar Rao, Hamid R. Arabnia. 85-90
- On Increasing the Observability of Modern MicroprocessorsHector Arteaga, Hussain Al-Asaad. 91-96
- DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-ChipJin Liu, José G. Delgado-Frias. 97-103
- On-Chip Split Shared Data Bus Architecture for SoCYil Suk Yang, Tae Moon Roh, Dae Woo Lee, Woo Hyun Kwon, Jongdae Kim. 104-108
- Design for Test Methodology for the IBM PowerPC 440 Embedded CoreWaleed Al-Assadi, Thomas Dick. 109-114
- Using a VHDL Testbench for Transistor-Level Simulation and Energy CalculationAnshul Singh, Scott C. Smith. 115-121
- NetSin: An Object-Oriented Architectural Simulator SuiteDavid Zier, Jarrod Nelson, Ben Lee. 122-128
- A Novel Functional Testing and Verification Technique for Logic CircuitsHussain Al-Asaad, Ganesh Valliappan, Lourdes Ramirez. 129-135
- Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAsJaafar Alghazo, Nazeih Botros. 136-142
- Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiencyArun Vijayaraghavan, M. Kannan, R. Seshasayanan. 143-152
- Possibility and Limitation of a Hardware-Assisted Data Prefetching Framework Using Off-Line Training of Markovian PredictorsJinwoo Kim, Kiran Puttaswamy. 153-158
- A Symmetric Differential Clock Generator for Bit-Serial HardwareMitchell J. Myjak, José G. Delgado-Frias. 159-164
- Design for A Fast And Low Power 2 s Complement MultiplierHimanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia. 165-167
- An Operand Status Based Instruction Steering Scheme for Clustered ArchitecturesYukinori Sato, Ken-ichi Suzuki, Tadao Nakamura. 168-174
- On Operating System Basic Building BlocksMartin Uhl. 175-184
- Space and Time Efficient Lottery SchedulingDaniel Pittman, Dennis Edwards. 185-190
- A Pipelined Multiplier Using A Hybrid Wave-Pipelining SchemeSuryanarayana Tatapudi, José G. Delgado-Frias. 191-197
- Minimal Steiner Trees in X Architecture with ObstaclesChung-Chin Luo, Yuan-Shin Hwang, Gene Eu Jan. 198-203
- Low-Power Data Address Bus Encoding MethodWei-Hao Chiao, Tsung-Hsi Weng, Jean Jyh-Jiun Shann, Chung-Ping Chung, Jimmy Lu. 204-210
- Low-Power Branch PredictionYau-Chong Hu, Wei-Hau Chiao, Jean Jyh-Jiun Shann, Chung-Ping Chung, Wen-Feng Chen. 211-217
- Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous MultipliersJiann S. Yuan, Jia Di. 218-223
- Completely Redundant Modular Exponentiation by Operand ChangingViktor Bunimov, Manfred Schimmler. 224-232
- Use of Kernel (Regression) Based Methods for Sensor ValidationAlexander Usynin, Wesley Hines. 233-239
- Spectral Decomposition and Reconstruction of Telemetry Signals from Enterprise Computing SystemsKenny C. Gross, Eugenio Schuster. 240-246
- Monte Carlo Simulation For Optimized Sensitivity of Online Proactive Fault Monitoring SchemesKalyan Vaidyanathan, Kenny C. Gross. 247-252
- A System-on-Chip Approach to Intelligent Traffic Signal ControlHsun-Jung Cho, Ming-Te Tseng. 253