A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture - researchr publication authors

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Syed Masood Ali, Rabin Raut, Mohamad Sawan. A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture. In Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada. pages 123-126, IEEE Computer Society, 2005. [doi]

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