Syed Masood Ali, Rabin Raut, Mohamad Sawan. A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture. In Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada. pages 123-126, IEEE Computer Society, 2005. [doi]
@inproceedings{AliRS05,
title = {A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture},
author = {Syed Masood Ali and Rabin Raut and Mohamad Sawan},
year = {2005},
doi = {10.1109/IWSOC.2005.22},
url = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.22},
tags = {architecture},
researchr = {https://researchr.org/publication/AliRS05},
cites = {0},
citedby = {0},
pages = {123-126},
booktitle = {Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada},
publisher = {IEEE Computer Society},
isbn = {0-7695-2403-6},
}