Massimo Alioto, Gaetano Palumbo. Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. In Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido, editors, Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002. Volume 2451 of Lecture Notes in Computer Science, pages 429-437, Springer, 2002. [doi]
Abstract is missing.