High Performance VLSI Architecture Design for H.264 CAVLC Decoder

Mythri Alle, Jayanta Biswas, S. K. Nandy. High Performance VLSI Architecture Design for H.264 CAVLC Decoder. In 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA. pages 317-322, IEEE Computer Society, 2006. [doi]

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