A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS

Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa. A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS. In 43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017, Leuven, Belgium, September 11-14, 2017. pages 151-154, IEEE, 2017. [doi]

@inproceedings{AlonsoMM17,
  title = {A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS},
  author = {Abdel Martinez Alonso and Masaya Miyahara and Akira Matsuzawa},
  year = {2017},
  doi = {10.1109/ESSCIRC.2017.8094548},
  url = {https://doi.org/10.1109/ESSCIRC.2017.8094548},
  researchr = {https://researchr.org/publication/AlonsoMM17},
  cites = {0},
  citedby = {0},
  pages = {151-154},
  booktitle = {43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017, Leuven, Belgium, September 11-14, 2017},
  publisher = {IEEE},
  isbn = {978-1-5090-5025-3},
}