Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture - researchr publication authors

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Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno. Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany. pages 62-63, IEEE Computer Society, 2005. [doi]

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