Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno. Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany. pages 62-63, IEEE Computer Society, 2005. [doi]
@inproceedings{AmoryLMM05,
title = {Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture},
author = {Alexandre M. Amory and Marcelo Lubaszewski and Fernando Gehm Moraes and Edson I. Moreno},
year = {2005},
doi = {10.1109/DATE.2005.304},
url = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.304},
tags = {rule-based, architecture, testing, reuse},
researchr = {https://researchr.org/publication/AmoryLMM05},
cites = {0},
citedby = {0},
pages = {62-63},
booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany},
publisher = {IEEE Computer Society},
isbn = {0-7695-2288-2},
}