Formal Verification: A Significant Step Towards Zero Deffect VLSI Design

François Anceau. Formal Verification: A Significant Step Towards Zero Deffect VLSI Design. In Gerhard Ritter, editor, Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28 - September 1, 1989. pages 528, North-Holland/IFIP, 1989.

Abstract

Abstract is missing.