Yoshimichi Andoh, Soichiro Suzuki, Satoshi Ohshima, Tatsuya Sakashita, Masao Ogino, Takahiro Katagiri, Noriyuki Yoshii, Susumu Okazaki. A thread-level parallelization of pairwise additive potential and force calculations suitable for current many-core architectures. The Journal of Supercomputing, 74(6):2449-2469, 2018. [doi]
Abstract is missing.