Theodoros Antonakopoulos, Nick Kanopoulos. Multiple boundary scan-paths for minimizing circuit-board test-application time. Journal of Systems Architecture, 40(6):377-386, 1994. [doi]
@article{AntonakopoulosK94,
title = {Multiple boundary scan-paths for minimizing circuit-board test-application time},
author = {Theodoros Antonakopoulos and Nick Kanopoulos},
year = {1994},
doi = {10.1016/0165-6074(94)90104-X},
url = {http://dx.doi.org/10.1016/0165-6074(94)90104-X},
tags = {testing},
researchr = {https://researchr.org/publication/AntonakopoulosK94},
cites = {0},
citedby = {0},
journal = {Journal of Systems Architecture},
volume = {40},
number = {6},
pages = {377-386},
}