Evaluation of low power consumption network on chip routing architecture

T. S. Arulananth, M. Baskar, Udhaya Sankar S. M, R. Thiagarajan, G. Arul Dalton, Pasupuleti Raja Rajeshwari, Aruru Sai Kumar, Suresh A. Evaluation of low power consumption network on chip routing architecture. Microprocessors and Microsystems, 82:103809, 2021. [doi]

Abstract

Abstract is missing.