Sameh W. Asaad, Kevin W. Warren. Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience. In Reiner W. Hartenstein, Andres Keevallik, editors, Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL 98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings. Volume 1482 of Lecture Notes in Computer Science, pages 278-287, Springer, 1998. [doi]
Abstract is missing.