Vivek Asthana, Malathi Kar, Jean Jimenez, Sébastien Haendler, Philippe Galy. 6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology. In Proceedings of 2013 International Conference on IC Design & Technology, ICICDT 2013, Pavia, Italy, May 29-31, 2013. pages 89-92, IEEE, 2013. [doi]
@inproceedings{AsthanaKJHG13,
title = {6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology},
author = {Vivek Asthana and Malathi Kar and Jean Jimenez and Sébastien Haendler and Philippe Galy},
year = {2013},
doi = {10.1109/ICICDT.2013.6563310},
url = {http://dx.doi.org/10.1109/ICICDT.2013.6563310},
researchr = {https://researchr.org/publication/AsthanaKJHG13},
cites = {0},
citedby = {0},
pages = {89-92},
booktitle = {Proceedings of 2013 International Conference on IC Design & Technology, ICICDT 2013, Pavia, Italy, May 29-31, 2013},
publisher = {IEEE},
isbn = {978-1-4673-4740-2},
}