Abstract is missing.
- Complex trade-offs - Enablement of moore and more than mooreDirk Wristers. 1-2 [doi]
- Technology push or marketing pull?Bruno Murari. 3-4 [doi]
- The FASTER vision for designing dynamically reconfigurable systemsMarco D. Santambrogio, Christian Pilato, Dionisios N. Pnevmatikatos, Kyprianos Papadimitriou, Dirk Stroobandt, Donatella Sciuto. 5-8 [doi]
- An efficient metric of setup time for pulsed flip-flops based on output transition timeSebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat. 9-12 [doi]
- Balanced stochastic truncation of coupled 3D interconnectAmir Zjajo, Nick van der Meijs, Rene van Leuken. 13-16 [doi]
- Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flopsInhak Han, Youngsoo Shin. 17-20 [doi]
- Exploration of different implementation styles for graphene-based reconfigurable gatesSandeep Miryala, Andrea Calimera, Massimo Poncino, Enrico Macii. 21-24 [doi]
- Improved modeling of isolated EDMOS in advanced CMOS technologiesAntoine Litty, Sylvie Ortolland, Sorin Cristoloveanu, Helene Beckrich Ros, Dominique Golanski. 25-28 [doi]
- Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact modelsPlamen Asenov, David New, Dave Reid, Campbell Millar, Scott Roy, Asen Asenov. 29-32 [doi]
- Convolution/deconvolution SRAM analyses for complex gamma mixtures RTN distributionsWorawit Somha, Hiroyuki Yamauchi. 33-36 [doi]
- Accelerated reliability testing of flash memory: Accuracy and issues on a 45nm NOR technologyMarcello Calabrese, Carmine Miccoli, Christian Monzio Compagnoni, Luca Chiavarone, Silvia Beltrami, Andrea Parisi, Sebastiano Bartolone, Andrea L. Lacaita, Alessandro S. Spinelli, Angelo Visconti. 37-40 [doi]
- Evaluating analog circuit performance in light of MOSFET aging at different time scalesHusni M. Habal, Helmut E. Graeb. 41-44 [doi]
- Process variation-tolerant 3D microprocessor design: An efficient architectural solutionJoonho Kong, Sung Woo Chung. 45-48 [doi]
- Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technologyGuillaume Moritz, Bastien Giraud, Jean-Philippe Noel, David Turgis, Anuj Grover. 53-56 [doi]
- A capacitively coupled clock distribution network with correction for process dependent skewDyuthi Kishan, Maryam Shojaei Baghini, Dinesh Kumar Sharma. 57-60 [doi]
- Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuitsShao-Yu Yang, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang. 61-64 [doi]
- Effective channel length of MOSFET with haloKazuo Terada, Kazuhiko Sanai, Shouhei Matsuoka, Katsuhiro Tsuji. 65-68 [doi]
- Impact of precursors choice on characteristics of PEALD SiN for spacer applicationsD. H. Triyoso, K. Hempel, S. Ohsiek, J. Shu, J. K. Schaeffer, M. Lenski. 69-72 [doi]
- Quantum confinement effect in strained-Si1-xGex double-gate tunnel field-effect transistorsNguyen Dang Chien, Chun-Hsing Shih, Luu The Vinh, Nguyen Van Kien. 73-76 [doi]
- Status and perspectives of embedded Non-Volatile memoriesAlfonso Maurelli. 77-80 [doi]
- A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuitsSanthosh Onkaraiah, Marc Belleville, Marina Reyboz, Fabien Clermidy, Elisa Vianello, Jean Michel Portal, Christophe Muller. 81-84 [doi]
- A compact model of hafnium-oxide-based resistive random access memoryFrancesco Maria Puglisi, Paolo Pavan, Andrea Padovani, Luca Larcher. 85-88 [doi]
- 6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technologyVivek Asthana, Malathi Kar, Jean Jimenez, Sébastien Haendler, Philippe Galy. 89-92 [doi]
- Impact of the leadframe profile on the occurrence of passivation cracks of plastic-encapsulated electronic power devicesJan Ackaert, Aditi Malik, Daniel Vanderstraeten. 93-96 [doi]
- High voltage operational amplifier and high voltage transceiver using 0.25 µm 60V BCD process for Battery Management SystemsChih-Lin Chen, Yi-Lun Wu, Chun-Ying Juan, Chua-Chin Wang. 97-100 [doi]
- Improved deep trench isolation breakdown voltage for SmartMOSThuy Dao, Todd Roggenbauer, Gordon Boyd. 101-104 [doi]
- High-voltage integrated Class-B amplifier for ultrasound transducersDario Bianchi, Fabio Quaglia, Andrea Mazzanti, Francesco Svelto. 105-108 [doi]
- Silicon-based quantum computationStephanie Simmons. 109-114 [doi]
- Dual-gate junction-less FET-detection for in-plane nano-electro-mechanical resonatorsFaezeh Arab Hassani, Hiroshi Mizuta, Yoshishige Tsuchiya, Hiroshi Mizuta, Cecilia Dupre, Eric Ollier, Sebastian T. Bartsch, Adrian Mihai Ionescu. 115-118 [doi]
- Automatic trimming procedure to enhance the accuracy of on-chip analog pulse generatorsErika Covi, Alessandro Cabrini, Guido Torelli. 119-122 [doi]
- Analog to digital converters on plastic foilsSahel Abdinia, Daniele Raiteri, S. Jacob, Romain Coppard, Pieter van Lieshout, Giuseppe Palmisano, Antonino Scuderi, Arthur H. M. van Roermund, Eugenio Cantatore. 123-126 [doi]
- High-swing buffer for programmable resistive memoriesErika Covi, Alessandro Cabrini, Guido Torelli. 127-130 [doi]
- Biosequences analysis on NanoMagnet LogicJ. Wang, Marco Vacca, Mariagrazia Graziano, M. RuoRoch, Maurizio Zamboni. 131-134 [doi]
- Towards minimum power analog filtersAndrea Baschirotto, Marcello De Matteis, Stefano D'Amico. 135-138 [doi]
- A 32-channel 12-bits single slope A-to-D converter for LHC environmentTommaso Vergine, Marcello De Matteis, Stefano D'Amico, Vincenzo Chironi, A. Marchioro, K. Kloukinas, Andrea Baschirotto. 139-142 [doi]
- A 14-bit extended-range incremental ΣΔ ADC matlab-model based on 90nm CMOS-technologyD. Cavallo, Marcello De Matteis, M. Ronchi, Elio Guidetti, G. Leggeri, Andrea Baschirotto. 143-146 [doi]
- A low-power CMOS 0.13 µm Charge-Sensitive Preamplifier for GEM detectorsAlessandro Pezzotta, Andrea Costantini, Marcello De Matteis, Stefano D'Amico, G. Gorini, F. Murtas, Andrea Baschirotto. 147-150 [doi]
- Design of high-order class-D audio amplifiersDavide Cartasegna, Piero Malcovati, Lorenzo Crespi, Kyehyung Lee, Andrea Baschirotto. 151-154 [doi]
- A 10Bit, 10MS/s, low power cyclic ADCChien-Hung Chen, Wei-Zen Chen. 155-158 [doi]
- A 34µW 75dB-dynamic-range CMOS analog front-end for intelligent tyre sensor networkMarcello De Matteis, Tommaso Vergine, M. Sabatini, Andrea Baschirotto. 163-166 [doi]
- Breast cancer detection based on an UWB imaging system: Receiver design and simulationsXiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni. 167-170 [doi]
- A dual-band balun LNA resilient to 5-6 GHz WLAN blockers for IR-UWB in 65nm CMOSVincenzo Chironi, Stefano D'Amico, Marcello De Matteis, Andrea Baschirotto. 171-174 [doi]
- Design and modeling of passive mixer-first receivers for millimeter-wave applicationsAnna Moroni, Danilo Manstretta. 175-178 [doi]
- Noise optimization of a broadband LNA for tuner applicationsH. Gul, A. Simin. 179-182 [doi]
- Characterization and modeling of depletion-type nMOS transistors for RF switches with zero power consumption in ON-stateCristian Andrei, Denis Raoulx, Guy Imbert, Bart Hovens, Andrea Scarpa. 183-186 [doi]
- High-speed and highly accurate evaluation of electrical characteristics in MOSFETsAkinobu Teramoto, Shigetoshi Sugawa, Tadahiro Ohmi. 187-190 [doi]
- Atomistic simulations of plasma process-induced Si substrate damage - Effects of substrate bias-power frequencyAsahiko Matsuda, Yoshinori Nakakubo, Yoshinori Takao, Koji Eriguchi, Kouichi Ono. 191-194 [doi]
- Improvement of gate disturb degradation in SONOS FETs for Vth mismatch compensation in CMOS analog circuitsMasamichi Suzuki, Atsuhiro Kinoshita, Yuichiro Mitani. 195-198 [doi]
- ESD protection using BIMOS transistor in 100 GHz RF application for advanced CMOS technologyPhilippe Galy, T. Lim, Jean Jimenez, Boris Heitz, Ph. Benech, J. M. Fournier, D. Marin-Cudraz. 199-202 [doi]
- The DOME embedded 64 bit microserver demonstratorRonald P. Luijten, Andreas C. Döring. 203-206 [doi]
- A fast CAM-based Watermarking extraction on FPGADuc-Hung Le, Tran Bao Thuong Cao, Katsumi Inoue, Cong-Kha Pham. 207-210 [doi]
- 2C System-on-Chip for bi-dimensional gas-sensor arrays providing extended dynamic-range A/D conversion and row temperature regulationFabrizio Conso, Marco Grassi, C. De Berti, Piero Malcovati, Andrea Baschirotto. 211-214 [doi]
- Bidirectional interconnect design for low latency high bandwidth NoCR. Kumar, Hrishikesh Deshpande, Gwan S. Choi, Alexander Sprintson, Paul Gratz. 215-218 [doi]
- TSV count minimization and thermal analysis for 3D Tree-based FPGAVinod Pangracious, Habib Mehrez, Zied Marrakchi. 223-226 [doi]
- High-density capacitors for SiP and SoC applications based on three-dimensional integrated metal-isolator-metal structuresWenke Weinreich, Matthias Rudolph, Johannes Koch, Jan Paul, Konrad Seidel, Stefan Riedel, Jonas Sundqvist, Katja Steidel, Manuela Gutsch, Volkhard Beyer, Christoph Hohle. 227-230 [doi]
- Smart Stacking™ and Smart Cut™ technologies for wafer level 3D integrationMariam Sadaka, Ionut Radu, Chrystelle Lagahe-Blanchard, Léa Di Cioccio. 231-234 [doi]
- Back-end 3D integration of HfO2-based RRAMs for low-voltage advanced IC digital designElisa Vianello, O. Thomas, M. Harrand, Santhosh Onkaraiah, T. Cabout, B. Traore, T. Diokh, Houcine Oucheikh, Luca Perniola, Gabriel Molas, Philippe Blaise, J.-F. Nodin, E. Jalaguier, Barbara De Salvo. 235-238 [doi]