SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI Circuits - researchr publication bibtex

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Abhaya Asthana, Mike Laznovsky, Boyd Mathews. SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI Circuits. In VLSI Design. pages 33-38, 1994.

@inproceedings{AsthanaLM94,
  title = {SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI Circuits},
  author = {Abhaya Asthana and Mike Laznovsky and Boyd Mathews},
  year = {1994},
  researchr = {https://researchr.org/publication/AsthanaLM94},
  cites = {0},
  citedby = {0},
  pages = {33-38},
  booktitle = {VLSI Design},
}

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