400 Gb/s Programmable Packet Parsing on a Single FPGA

Michael Attig, Gordon J. Brebner. 400 Gb/s Programmable Packet Parsing on a Single FPGA. In 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), Brooklyn, NY, USA, October 3-4, 2011. pages 12-23, IEEE, 2011. [doi]

@inproceedings{AttigB11,
  title = {400 Gb/s Programmable Packet Parsing on a Single FPGA},
  author = {Michael Attig and Gordon J. Brebner},
  year = {2011},
  doi = {10.1109/ANCS.2011.12},
  url = {http://doi.ieeecomputersociety.org/10.1109/ANCS.2011.12},
  researchr = {https://researchr.org/publication/AttigB11},
  cites = {0},
  citedby = {0},
  pages = {12-23},
  booktitle = {2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), Brooklyn, NY, USA, October 3-4, 2011},
  publisher = {IEEE},
  isbn = {978-1-4577-1454-2},
}