45nm high-k + metal gate strain-enhanced CMOS transistors

Chris Auth. 45nm high-k + metal gate strain-enhanced CMOS transistors. In Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008. pages 379-386, IEEE, 2008. [doi]

@inproceedings{Auth08,
  title = {45nm high-k + metal gate strain-enhanced CMOS transistors},
  author = {Chris Auth},
  year = {2008},
  doi = {10.1109/CICC.2008.4672101},
  url = {http://dx.doi.org/10.1109/CICC.2008.4672101},
  researchr = {https://researchr.org/publication/Auth08},
  cites = {0},
  citedby = {0},
  pages = {379-386},
  booktitle = {Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008},
  publisher = {IEEE},
  isbn = {978-1-4244-2018-6},
}