Manohar Ayinala, Keshab K. Parhi. Parallel pipelined FFT architectures with reduced number of delays. In Erik Brunvard, Ken Stevens, Joseph R. Cavallaro, Tong Zhang 0002, editors, Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake Cit, UT, USA, May 3-4, 2012. pages 63-66, ACM, 2012. [doi]
Abstract is missing.