Delay partitioning helps reducing variability in 3DVLSI

A. Ayres, Olivier Rozeau, B. Borot, Laurent Fesquet, Maud Vinet. Delay partitioning helps reducing variability in 3DVLSI. In nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016. pages 75-78, IEEE, 2016. [doi]

Authors

A. Ayres

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Olivier Rozeau

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B. Borot

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Laurent Fesquet

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Maud Vinet

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