Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne. Feasible Delay Bound Definition. In Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes, editors, SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC 01), December 3-5, 2001, Montpellier, France. Volume 218 of IFIP Conference Proceedings, pages 325-335, Kluwer, 2001.
@inproceedings{AzemardAMA01,
title = {Feasible Delay Bound Definition},
author = {Nadine Azémard and M. Aline and Philippe Maurine and Daniel Auvergne},
year = {2001},
researchr = {https://researchr.org/publication/AzemardAMA01},
cites = {0},
citedby = {0},
pages = {325-335},
booktitle = {SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC 01), December 3-5, 2001, Montpellier, France},
editor = {Michel Robert and Bruno Rouzeyre and Christian Piguet and Marie-Lise Flottes},
volume = {218},
series = {IFIP Conference Proceedings},
publisher = {Kluwer},
isbn = {1-4020-7148-5},
}