Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi. Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator. IEICE Transactions, 97-C(6):546-556, 2014. [doi]
@article{AzumaSMNKTMHNTIHMETY14,
title = {Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator},
author = {Naoya Azuma and Shunsuke Shimazaki and Noriyuki Miura and Makoto Nagata and Tomomitsu Kitamura and Satoru Takahashi and Motoki Murakami and Kazuaki Hori and Atsushi Nakamura and Kenta Tsukamoto and Mizuki Iwanami and Eiji Hankui and Sho Muroga and Yasushi Endo and Satoshi Tanaka and Masahiro Yamaguchi},
year = {2014},
url = {http://search.ieice.org/bin/summary.php?id=e97-c_6_546},
researchr = {https://researchr.org/publication/AzumaSMNKTMHNTIHMETY14},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {97-C},
number = {6},
pages = {546-556},
}