Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients - researchr publication authors

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Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen. Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. In Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002. pages 399-404, ACM, 2002. [doi]

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