Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog Kyoon Jeong. A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. In ESSCIRC 2014 - 40th European Solid State Circuits Conference, Venice Lido, Italy, September 22-26, 2014. pages 447-450, IEEE, 2014. [doi]
@inproceedings{BaeJPCKJ14,
title = {A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line},
author = {Woo-Rham Bae and Gyu-Seob Jeong and Kwanseo Park and Sung-Yong Cho and Yoonsoo Kim and Deog Kyoon Jeong},
year = {2014},
doi = {10.1109/ESSCIRC.2014.6942118},
url = {http://dx.doi.org/10.1109/ESSCIRC.2014.6942118},
researchr = {https://researchr.org/publication/BaeJPCKJ14},
cites = {0},
citedby = {0},
pages = {447-450},
booktitle = {ESSCIRC 2014 - 40th European Solid State Circuits Conference, Venice Lido, Italy, September 22-26, 2014},
publisher = {IEEE},
isbn = {978-1-4799-5694-4},
}