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Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only)

Yu Bai, Abigail Fuentes, Mingjie Lin, Mike Riera. Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only). In Brad L. Hutchings, Vaughn Betz, editors, The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, Monterey, CA, USA, February 11-13, 2013. pages 273, ACM, 2013. [doi]

Authors

Yu Bai

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Abigail Fuentes

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Mingjie Lin

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Mike Riera

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