A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits - researchr publication related

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Xu Bai, Michitaka Kameyama. A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits. IEICE Transactions, 96-C(8):1083-1093, 2013. [doi]

The following publications are possibly variants of this publication:

Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair CircuitsNobuaki Okada, Michitaka Kameyama. ieicet, 93-D(8):2126-2133, 2010. [doi]

Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair CircuitsNobuaki Okada, Michitaka Kameyama. ismvl 2007: 25 [doi]

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its EvaluationNobuaki Okada, Michitaka Kameyama. ieicet, 91-C(9):1437-1443, 2008. [doi]

Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair CircuitHaque Mohammad Munirul, Michitaka Kameyama. ismvl 2006: 13 [doi]

Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair CircuitsNobuaki Okada, Michitaka Kameyama. mvl, 13(4-6):619-632, 2007. [doi]

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