Steven Bailey, Paul Rigge, Jaeduk Han, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic. A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. J. Solid-State Circuits, 54(10):2786-2801, 2019. [doi]
@article{BaileyRHLCMWMIW19,
title = {A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance},
author = {Steven Bailey and Paul Rigge and Jaeduk Han and Richard Lin and Eric Chang and Howard Mao and Zhongkai Wang and Chick Markley and Adam M. Izraelevitz and Angie Wang and Nathan Narevsky and Woo-Rham Bae and Steve Shauck and Sergio Montano and Justin Norsworthy and Munir Razzaque and Wen Hau Ma and Akalu Lentiro and Matthew Doerflein and Darin Heckendorn and Jim McGrath and Franco DeSeta and Ronen Shoham and Mike Stellfox and Mark Snowden and Joseph Cole and Dan Fuhrman and Brian C. Richards and Jonathan Bachrach and Elad Alon and Borivoje Nikolic},
year = {2019},
doi = {10.1109/JSSC.2019.2924090},
url = {https://doi.org/10.1109/JSSC.2019.2924090},
researchr = {https://researchr.org/publication/BaileyRHLCMWMIW19},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {54},
number = {10},
pages = {2786-2801},
}