2, 0.44-pJ/b, 2-Gb/s All-Digital Fully Synthesizable CDR for Serial Links Using Single-Phase Input Clock

Ankur Bal, Rupesh Singh, Aradhana Kumari, Vikas Dhanda. 2, 0.44-pJ/b, 2-Gb/s All-Digital Fully Synthesizable CDR for Serial Links Using Single-Phase Input Clock. IEEE Trans. Circuits Syst. II Express Briefs, 69(10):4073-4077, 2022. [doi]

Authors

Ankur Bal

This author has not been identified. Look up 'Ankur Bal' in Google

Rupesh Singh

This author has not been identified. Look up 'Rupesh Singh' in Google

Aradhana Kumari

This author has not been identified. Look up 'Aradhana Kumari' in Google

Vikas Dhanda

This author has not been identified. Look up 'Vikas Dhanda' in Google