Ankur Bal, Rupesh Singh, Aradhana Kumari, Vikas Dhanda. 2, 0.44-pJ/b, 2-Gb/s All-Digital Fully Synthesizable CDR for Serial Links Using Single-Phase Input Clock. IEEE Trans. Circuits Syst. II Express Briefs, 69(10):4073-4077, 2022. [doi]
Abstract is missing.