Low voltage CMOS timing generator using array of digital delay lock loops - researchr publication

researchr

You are not signed in
Sign in
Sign up

S. Balaji, K. S. Srinivasan. Low voltage CMOS timing generator using array of digital delay lock loops. In 55th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, USA, August 5-8, 2012. pages 242-245, IEEE, 2012. [doi]

Abstract is missing.

runs on WebDSL