Junction leakage current degradation under high temperature reverse-bias stress induced by band-defect-band tunnelling in power VDMOS

Giacomo Barletta, Giuseppe CurrĂ². Junction leakage current degradation under high temperature reverse-bias stress induced by band-defect-band tunnelling in power VDMOS. Microelectronics Reliability, 45(5-6):994-999, 2005. [doi]

@article{BarlettaC05,
  title = {Junction leakage current degradation under high temperature reverse-bias stress induced by band-defect-band tunnelling in power VDMOS},
  author = {Giacomo Barletta and Giuseppe CurrĂ²},
  year = {2005},
  doi = {10.1016/j.microrel.2004.11.008},
  url = {http://dx.doi.org/10.1016/j.microrel.2004.11.008},
  researchr = {https://researchr.org/publication/BarlettaC05},
  cites = {0},
  citedby = {0},
  journal = {Microelectronics Reliability},
  volume = {45},
  number = {5-6},
  pages = {994-999},
}