Real-Time Visual Saliency Architecture for FPGA With Top-Down Attention Modulation

Francisco Barranco, Javier Diáz, Begona Pino, Eduardo Ros. Real-Time Visual Saliency Architecture for FPGA With Top-Down Attention Modulation. IEEE Trans. Industrial Informatics, 10(3):1726-1735, 2014. [doi]

Abstract

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