An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s Wireline Systems

Richard Barrie, Ming Yang 0005, Hossein Shakiba, Anthony Chan Carusone. An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s Wireline Systems. In 67th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2024, Springfield, MA, USA, August 11-14, 2024. pages 282-285, IEEE, 2024. [doi]

Abstract

Abstract is missing.